Compare FALCON-A
eith SRC bits of MAR and MBR?
Answer:-
Memory
Address Register (MAR) and Memory Buffer Register (MBR) are also of 16-bits while
in SRC these are of 32-bits. MAR and MBR are dual port registers. At one side
they are connected to internal bus and at other side to external memory in
order to point to a particular address for reading or writing data from or to
the memory and MBR would get the data from the memory.
Difference b/w
executing machine instructions with and without pipelining?
Answer:
We start by assuming that a given processor can be split in
to five different stages as shown in the diagram below, and as explained later
in this section. Each stage receives its input from the previous stage and
provides its result to the next stage. It can be easily seen from the diagram that
in case of a non pipelined machine there is a single instruction add r4, r2, r3
being processed at a given time, while in a pipelined machine, five different instructions
are being processed simultaneously. An implied assumption in this case is that
at the end of each stage, we have some sort of a storage place (like temporary registers)
to hold the results of the present stage till they are used by the next stage.
Structural RTL for “out” out, ra, c2?
Structural RTL for “out” out, ra, c2?
Answer:
In which
stage of pipeline,the effective memory Address is calculated?(Answer: ALU Operation)
Answer:
1. Instruction fetched
1. Instruction fetched
2. Instruction decode/operand fetch
3. ALU operation
4. Memory access
5. Register Write
Structural RTL for “un conditional jump” jump [ra,c2]?
Answer:
Difference
pipelining and instruction level parallelism?
Answer:
Write structural RTL for shift ra ,rb and cl
Answer:
Answer:
Describe 5 examples of exception when they occur?
Answer:
Program Exceptions
These
are exceptions raised during the process of decoding and executing the
instruction.
Examples are illegal instruction, raised in response to executing an
instruction
which does not belong to the instruction set. Another example would
be
the privileged instruction exception.
•
Hardware Exceptions
There
are various kinds of hardware exceptions. An example would be of a timer
which
raises an exception when it has counted down to zero.
•
Trace and debugging Exceptions
Variable
trace and debugging is a tricky task. An easy approach to make it
possible
is through the use of traps. The exception handler which would be called
after
each instruction execution allows examination of the program variables.
•
Nonmaskable Exceptions
These
are high priority exceptions reserved for events with catastrophic
consequences
such as power loss. These exceptions cannot be suppressed by the
processor
under any condition. In case of a power loss the processor might try to
save
the system state to the hard drive, or alert an alternate power supply.
•
Interrupts (External Exceptions)
Exception
handlers may be written for external interrupts, thus allowing programs
to
respond to external events such as keyboard or mouse events.
Write RTL and control signal notation for following add
instruction:
add ra, rb, rc;
Answer
Structural RTL for in ra, c2?
Answer:
What function is performed by the reset operation of a
processor and differentiate Hard reset and Soft reset.
Answer:
Briefly explain the types of branch?
Answer:
Branch:
Branch
instruction branches to address In Rb depending on the condition in
rc.
Branch with link:
Branch
link branches to address in Rb depending on condition in rc Additionally, it
copies the PC into ra before branching.
Which register is used to hold source operand and the result
of the arithmetic or logical operation?
Answer:
Accumulator register
differentiate
b/w MBR and MAR?
Answer:
relation b/w data path and control unit?
Answer:
Differentiate between hardwired and microcoded
control system?
Answer:
what are three categories of pipeline Hazards?
Explain
[c <-- A+C2 (Sign extend);] ?
Answer:
In this
step we would add the constant c2 after sign extension to the contents of
temporary register A. As a result we would have the effective address in the
buffer register C, to which we need to jump.
Write approaches to achieve instruction level parallelism?
Answer:
The two approaches to achieve instruction-level
parallelism are
–
Superscalar Architecture
A
scalar processor that can issue multiple instructions simultaneously is said to
be
superscalar
–
VLIW Architecture
A
VLIW processor is based on a very long instruction word. VLIW relies on
instruction
scheduling by the compiler. The compiler forms instruction packets which can
run
in parallel without dependencies.
Write
the structural RTL for the mov immediate instruction for the mov immediate
instruction for uni-bus data path implementation Movi ra,c2?
Answer:
Write the related timing steps requirements and
data path implementations of Instruction Fetch procedure using structural RTL?
Write the Structural RTL for the "mov"
instruction i.e. mov ra, rb. ?
Answer:
Which
register holds the instruction that is being executed?
Answer:
The
instruction that is to be executed is fetched from the memory
and
temporarily stored in a CPU register, called the instruction register (IR). The
instruction
register holds the instruction while it is decoded and executed by the central processing
unit (CPU) of the computer.
steps to
increase processors throughput?
Answer:
Increasing a processor’s throughput
There
are two ways to increase the number of instructions executed in a given time by
a
processor
•
By increasing the clock speed
•
By increasing the number of instructions
that can execute in parallel
Increasing the clock speed
•
Increasing the clock speed is an IC design issue and depends on the
advancements in
chip
technology.
•
The computer architect or logic designer can not thus manipulate clock speeds
to
increase
the throughput of the processor.
Increasing parallel execution of instructions
The
computer architect cannot increase the clock speed of a microprocessor however
he/she
can increase the number of instructions processed per unit time. In pipelining
we
discussed
that a number of instructions are executed in a staggered fashion, i.e. various
instructions
are simultaneously executing in different segments of the pipeline. Taking
this
concept a step further we have multiple data paths hence multiple pipelines can
execute
simultaneously. There are two main categories of these kinds of parallel
instruction
processors VLIW (very long instruction word) and superscalar.
Make structural rtl for register to register add instruction?
Answer:
role of timing step generator?
Define Lmbr?
Answer:
RTL for call ra,rb?
Answer:
Write
five stages of pipeline and their registers which use in pipeline stages step
by step?
Answer:
Name of 3 step of designing and implementation a pipeline
machine?
Answer:
1. Adapting the instructions to pipelined execution
The
instruction set of a non-pipelined processor is generally different from that
of a
pipelined
processor. The instructions in a pipelined processor should have clear and
definite
phases, e.g., add r1, r2, r3. To execute this instruction, the processor must first
fetch
it from memory, after which it would need to read the registers, after which
the
actual
addition takes place followed by writing the results back to the destination
register.
Usually
register-register architecture is adopted in the case of pipelined processors
so that
there
are no complex instructions involving operands from both memory and registers.
An
instruction like add r1, r2, a would need to execute the memory access stage before
the
operands may be fed to the ALU. Such flexibility is not available in a
pipelined
architecture.
2. Designing the pipelined data path
Once
a particular instruction set has been chosen, an appropriate data path needs to
be
designed
for the processor. The data path is a specification of the steps that need to
be
followed
to execute an instruction. Consider our two examples above
For
the instruction add r1, r2, r3: Instruction Fetch – Register
Read – Execute – Register Write,
whereas
for the instruction add r1, r2, a (remember a represents a memory address), we
have
Instruction Fetch – Register
Read – Memory Access – Execute – Register Write
The
data path is defined in terms of registers placed in between these stages. It
specifies
how
the data will flow through these registers during the execution of an
instruction. The
data
path becomes more complex if forwarding or bypassing mechanism is added to the
processor.
3. Generating control signals
Control
signals are required to regulate and direct the flow of data and instruction
bits
through
the data path. Digital logic is required to generate these control signals.
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